1. Field of the Invention
This invention relates to the testing of random access memories (RAMs), and, more particularly, is concerned with testing data lines of RAMs.
2. Description of the Prior Art
It is known, in microprocessor circuits including RAMs, to test the RAMs to check that they are operating correctly. Such tests may be administered as a post-assembly functionality check after a circuit board incorporating a RAM has been manufactured, or as a diagnostic check each time that the circuit is powered up.
As shown in FIG. 1, a typical RAM comprises data lines for connection to a data bus of a circuit (not shown) of which the RAM forms part or is to form part, address lines for connection to an address bus of the circuit, and an enable line for connection to the circuit for activation of the RAM.
FIG. 2 is a memory map of a typical RAM. The RAM has a plurality of address locations each having the capacity to store a word or byte comprising a number of bits equal to the number of data lines. By way of example, the memory map shown in FIG. 2 represents a RAM which has 64 address locations (numbered 0 to 63) each capable of storing an 8-bit word or byte. In this example, as shown in FIG. 1, the RAM has eight data lines. Also, since six bits are necessary to address 64 (=2.sup.6) address locations, the RAM has six address lines.
To comprehensively check the RAM, each data line, each address line and the enable line has to be tested. These tests are required to look for open circuits or short circuits to supply voltage or ground and open circuits or short circuits to any other of the above-mentioned lines.
Known RAM enable line and address line tests comprise filling each of the address locations with a test word, then reading the test words from each address location and checking that it is the same as the test words as written to the address location. The process is then repeated with another test word.
Testing of the data lines, with which the present invention is concerned, requires: (a) writing a test word into all of the address locations of the RAM; (b) reading the est word from all of the address locations of the RAM and checking that the test word as read from each of the address locations is the same as the test word written in; and (c) repeating steps (a) and (b) for a plurality of different test words.
Selection of the test words represents a problem. Clearly, the data lines could be tested with a high confidence of detecting all faults if all possible test words were used (though this involves the disadvantage of having to generate all of the many possible test words). In such a case, pursuing the above example of a RAM having 64 8-bit address locations, there are 256 (=2.sup.8) possible test words and each of these would have to be written to all address locations and then read from each address location and checked. If, for example, each of the 16,384 (=256.times.64) reading and checking operations took (say) about 5 microseconds, the total test time would be about 82 milliseconds. In most cases, such a total testing time would be acceptable. However, RAM is often used in much larger amounts. A typical modern microcomputer has at least about 512K of RAM, whereby the total testing time (again at a rate of 5 microseconds per operation) would be nearly eleven minutes and would therefore be prohibitively long. This would be even more clearly so in the case of a RAM having (as is often the case) more than 512K 8-bit address locations.